JPH0583190B2 - - Google Patents

Info

Publication number
JPH0583190B2
JPH0583190B2 JP61304676A JP30467686A JPH0583190B2 JP H0583190 B2 JPH0583190 B2 JP H0583190B2 JP 61304676 A JP61304676 A JP 61304676A JP 30467686 A JP30467686 A JP 30467686A JP H0583190 B2 JPH0583190 B2 JP H0583190B2
Authority
JP
Japan
Prior art keywords
impurity diffusion
diffusion region
region
transistor
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61304676A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63157462A (ja
Inventor
Junichi Nakao
Tomonori Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP61304676A priority Critical patent/JPS63157462A/ja
Publication of JPS63157462A publication Critical patent/JPS63157462A/ja
Publication of JPH0583190B2 publication Critical patent/JPH0583190B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/617—Combinations of vertical BJTs and only diodes

Landscapes

  • Bipolar Integrated Circuits (AREA)
JP61304676A 1986-12-20 1986-12-20 半導体装置 Granted JPS63157462A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61304676A JPS63157462A (ja) 1986-12-20 1986-12-20 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61304676A JPS63157462A (ja) 1986-12-20 1986-12-20 半導体装置

Publications (2)

Publication Number Publication Date
JPS63157462A JPS63157462A (ja) 1988-06-30
JPH0583190B2 true JPH0583190B2 (en]) 1993-11-25

Family

ID=17935883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61304676A Granted JPS63157462A (ja) 1986-12-20 1986-12-20 半導体装置

Country Status (1)

Country Link
JP (1) JPS63157462A (en])

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1230025B (it) * 1988-10-28 1991-09-24 Sgs Thomson Microelectronics Dispositivo darlington con transistore di estrazione ed emettitore ultraleggero e relativo procedimento di fabbricazione
JP4951851B2 (ja) * 2004-10-08 2012-06-13 パナソニック株式会社 半導体装置
JP5224690B2 (ja) * 2007-01-10 2013-07-03 株式会社三社電機製作所 トランジスタ

Also Published As

Publication number Publication date
JPS63157462A (ja) 1988-06-30

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees